Horizontal current bipolar transistor (HCBT) process variations for future RF BiCMOS applications

Two different process designs of horizontal current bipolar transistor (HCBT) technology suitable for future RF BiCMOS circuits are presented. The active transistor region is built in the defect-free sidewall of 900-nm-wide n-hills on a (110) wafer. The collector n-hill region is partially etched at the extrinsic base-collector periphery, whereas the extrinsic base is self-protected, resulting in reduced collector-base capacitance (C-BC) and minimized volume of the extrinsic regions. The effect of doping levels at different regions on the transistor performance is examined in the two process designs. The fabricated HCBTs exhibit cutoff frequencies (f(T)) from 19.2 to 25.6 GHz, maximum frequencies of oscillations (f(max)) from 32.2 to 39.6 GHz, and collector-emitter breakdown voltages (BVCEO) between 4 and 5.2 V, which are the highest fT and the highest fT center dot BVCEO product compared to existing silicon-on-insulator (SOI) lateral bipolar transistors (LBTs). The compact nature of the HCBT structure and low-cost technology make it suitable for integration with advanced pillar-like CMOS and SOI CMOS devices.