The GBT-SerDes ASIC prototype

被引：55

作者：

Moreira, P. ^{[1
]}

Baron, S. ^{[1
]}

Bonacini, S. ^{[1
]}

Cobanoglu, O. ^{[1
]}

Faccio, F. ^{[1
]}

Feger, S. ^{[1
]}

Francisco, R. ^{[1
]}

Gui, P. ^{[2
]}

Li, J. ^{[2
]}

Marchioro, A. ^{[1
]}

Paillard, C. ^{[1
]}

Porret, D. ^{[1
]}

Wyllie, K. ^{[1
]}

机构：

[1] CERN, CH-1211 Geneva 23, Switzerland

[2] So Methodist Univ, Dallas, TX 75275 USA

来源：

JOURNAL OF INSTRUMENTATION | 2010年 / 5卷

关键词：

VLSI circuits; Radiation-hard electronics; Analogue electronic circuits; Digital electronic circuits;

D O I：

10.1088/1748-0221/5/11/C11022

中图分类号：

TH7 [仪器、仪表];

学科分类号：

0804 ; 080401 ; 081102 ;

摘要：

In the framework of the GigaBit Transceiver project (GBT), a prototype, the GBTSerDes ASIC, was developed, fabricated and tested. To sustain high radiation doses while operating at 4.8Gb/s, the ASIC was fabricated in a commercial 130 nm CMOS technology employing radiation tolerant techniques and circuits. The transceiver serializes-deserializes the data, Reed-Solomon encodes and decodes the data and scrambles and descrambles the data for transmission over optical fibre links. This paper describes the GBT-SerDes architecture, and presents the test results.

引用

页数：8

共 8 条

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