Verilog-A Compact Model for a Novel Cu/SiO2/W Quantum Memristor

被引：0
|
作者：
Nandakumar, S. R. [1 ]
Rajendran, Bipin [1 ]
机构：
[1] New Jersey Inst Technol, Dept Elect & Comp Engn, Newark, NJ 07102 USA
来源：
2016 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES (SISPAD) | 2016年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, we develop a Verilog-A model for a memristive device that has shown non-volatile state transitions via half-integer quantized conductance states at room temperature and an on-off ratio of similar to 10(3). The model captures the geometrical evolution of a nano-filament and maps it to conductance levels in the equivalent electrical circuit, thereby accurately capturing the DC I-V and transient response of the device. The suitability of the model for circuit simulations is illustrated via a 4 x 4 crossbar array programming simulation in HSPICE which captures the multilevel programmability of the device.
引用
收藏
页码：169 / 172
页数：4
相关论文
共 50 条
  • [31] Verilog-A Compact Model for Oxide-based Resistive Random Access Memory(RRAM)
    Jiang, Zizhen
    Yu, Shimeng
    Wu, Yi
    Engel, Jesse H.
    Guan, Ximeng
    Wong, H. -S. Philip
    2014 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES (SISPAD), 2014, : 41 - 44
  • [32] 2D RRAM and Verilog-A model for Neuromorphic Computing
    Huang, Yifu
    Wu, Xiaohan
    Gu, Yuqian
    Ge, Ruijing
    Zhang, Jiahan
    Chang, Yao-Feng
    Akinwande, Deji
    Lee, Jack C.
    2021 IEEE 16TH NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE (NMDC 2021), 2021,
  • [33] Analysis of Parasitic Effects in Filamentary-Switching Memristive Memories Using an Approximated Verilog-A Memristor Model
    Lupo, Nicola
    Perez, Eduardo
    Wenger, Christian
    Maloberti, Franco
    Bonizzoni, Edoardo
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2019, 66 (05) : 1935 - 1947
  • [34] Verilog-A implementation of a double-gate junctionless compact model for DC circuit simulations
    Alvarado, J.
    Flores, P.
    Romero, S.
    Avila-Herrera, F.
    Gonzalez, V.
    Soto-Cruz, B. S.
    Cerdeira, A.
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2016, 31 (07)
  • [35] A Novel Nontraditional Approach to C2W Cu/SiO2 Hybrid Bonding
    Jiang, Han
    Liu, Ziyu
    Lin, Chen
    Li, Chuandong
    Ning, Zeyu
    Chen, Lin
    Xu, Jeff
    Sun, Qingqing
    2024 25TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, ICEPT, 2024,
  • [36] Bio-mimetic synaptic plasticity and learning in a sub-500 mV Cu/SiO2/W memristor
    Nandakumar, S. R.
    Rajendran, Bipin
    MICROELECTRONIC ENGINEERING, 2020, 226
  • [37] An enhanced Verilog-A compact model for bipolar RRAMs including transient thermal effects and series resistance
    Maldonado, D.
    Jimenez-Molinos, F.
    Roldan, J. B.
    Gonzalez, M. B.
    Campabadal, F.
    PROCEEDINGS OF THE 37TH CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (DCIS 2022), 2022, : 143 - 148
  • [38] A Compact IGBT Electro-Thermal Model in Verilog-A for Fast System-Level Simulation
    Lena, Davide
    Grosso, Michelangelo
    Bocca, Alberto
    Macii, Alberto
    Rinaudo, Salvatore
    PROCEEDINGS OF THE IECON 2016 - 42ND ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY, 2016, : 3793 - 3798
  • [39] A Unified Verilog-A Compact Model for Lateral Si Nanowire (NW) FET Incorporating Parasitics for Circuit Simulation
    Prakash, Om.
    Maheshwaram, S.
    Sharma, M.
    Bulusu, A.
    Saxena, A. K.
    Manhas, S. K.
    2016 20TH INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AND TEST (VDAT), 2016,
  • [40] Compact Verilog-A model of phase-change RAM transient behaviors for multi-level applications
    Jung, Chul-Moon
    Lee, Eun-Sub
    Min, Kyeong-Sik
    Kang, Sung-Mo
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2011, 26 (10)
12345