共 11 条
- [2] The digit parallel method for fast RNS to weighted number system conversion for specific moduli (2(k)-1,2(k),2(k)+1) [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1997, 44 (01): : 53 - 57
- [3] Garner HarveyL., 1959, IRE Transactions on Electronic Computers, VEC -8, P140, DOI DOI 10.1109/TEC.1959.5219515
- [4] Hwang K., 1979, Computer Arithmetic-Principles, Architecture And Design
- [5] Koren I., 1993, COMPUTER ARITHMETIC
- [6] AN RNS TO BINARY CONVERTER IN 2N + 1, 2N, 2N - 1 MODULI SET [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1992, 39 (07): : 480 - 482
- [7] AN RNS TO BINARY CONVERTER IN A 3 MODULI SET WITH COMMON FACTORS [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1995, 42 (04): : 298 - 301
- [8] Soderstrand M., 1986, RESIDUE NUMBER SYSTE
- [9] Szabo N.S., 1967, RESIDUE ARITHMETIC I
- [10] AN EFFICIENT RESIDUE-TO-DECIMAL CONVERTER [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1981, 28 (12): : 1164 - 1169