Low-Voltage 9T FinFET SRAM Cell for Low-Power Applications

被引：0

作者：

Moradi, Farshad ^{[1
]}

Tohidi, Mohammad ^{[1
]}

机构：

[1] Aarhus Univ, Dept Engn, Integrated & Elect Lab, Aarhus, Denmark

来源：

2015 28TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC) | 2015年

关键词：

SRAM; Write Margin; Read Static Noise Margin; CMOS; Low-Voltage;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a novel multi-threshold 9T-SRAM cell using FinFET technology with improved read and write margins in comparison with the standard 6T-SRAM cell is proposed. By the use of this bit-cell at supply voltage of 200mV (800mV), read and write margins are improved by 92% (97%) and 2X (40%), respectively. The proposed design operates at supply voltages lower than 300mV that results in a 3X lower power consumption compared to the standard 6T-SRAM cell.

引用

页码：149 / 153

页数：5