Design and Implementation of Histogram Equalization Enhancement Based on FPGA

被引：0

作者：

Jia, Zan ^{[1
]}

Ren, Wenping ^{[1
]}

Li, Peng ^{[1
]}

Chen, Zhijian ^{[1
]}

机构：

[1] Yunnan Univ, Sch Informat Sci & Engn, Kunming 650091, Peoples R China

来源：

15TH CONFERENCE ON THE WIRELESS ACROSS THE TAIWAN STRAITS, PROCEEDINGS | 2010年

关键词：

FPGA; histogram equalization; image;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

FPGA has an capability to process data in real-time and parallel. This paper introduces a design of FPGA-based image histogram equalization enhancement algorithm and makes it realize through improving effect of image. Compared with DSP circuit, FPGA has quick data processing ability that enable to speed up histogram equalization algorithm and meet real-time processing demand.

引用

页码：282 / 284

页数：3