Characterizing electron shower with CHARM®-2 wafers on Eaton NV-8200P medium current ion implanter

被引:0
|
作者
Reno, S [1 ]
Gonzalez, H [1 ]
Messick, C [1 ]
Lukaszek, W [1 ]
St Angelo, DA [1 ]
Becker, K [1 ]
Rogers, B [1 ]
Romanski, T [1 ]
机构
[1] Fairchild Semicond, W Jordan, UT 84088 USA
来源
1998 IEEE INTERNATIONAL INTEGRATED RELIABIILTY WORKSHOP FINAL REPORT | 1998年
关键词
D O I
10.1109/IRWS.1998.745374
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Avoiding gate oxide damage due to excessive wafer charging has always been an issue with high current implanters. On the other hand, whether it is caused by shrinking of device dimensions, or its use as a backup for high current applications, charging level awareness becomes the primary limiting factor for running higher beam currents in medium current implanters. Often times, a cautious approach results in lower machine throughput. To the present, flooding the wafer with low energy electrons from electron showers (E-Shower) has been the widely accepted means of reducing wafer charging. The effectiveness of the E-shower in reducing charging as a function of primary ion current has been investigated in Eaten's medium current ion implanter. Extensive testing included over 180 bare and photoresist coated CHARM(R)-2 charge monitors. Optimum shower settings will be presented and discussed in the light of CHARM-2 results and product split lot yields.
引用
收藏
页码:86 / 89
页数:4
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