A 132.6-GHz Phase-Locked Loop in 65 nm Digital CMOS

被引：7
|
作者：
Lin, Bo-Yu [1 ,2 ]
Liu, Shen-Iuan [1 ,2 ]
机构：
[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10617, Taiwan
[2] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2011年 / 58卷 / 10期
关键词：
Fourth-order LC ladder; injection-locked frequency divider (ILFD); phase-locked loop (PLL); voltage-controlled oscillator (VCO);
D O I：
10.1109/TCSII.2011.2164156
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A phase-locked loop (PLL) with the proposed voltage-controlled oscillator (VCO) and a divide-by-2 injection-locked frequency divider (ILFD) is fabricated in 65-nm digital CMOS technology. The proposed VCO and the divide-by-two ILFD operate at the higher and lower poles, respectively, of two fourth-order LC ladders. The frequency ratio between the VCO and its first divide-by-2 ILFD is kept by scaling the inductances and the capacitances. The design considerations of this VCO and the locking range of this ILFD are discussed. The measured locking range of this PLL is 132.1-132.6 GHz. It consumes 120.8 mW from 1.35-V supply, excluding the output buffers. The chip area is 0.96 x 0.92 mm(2).
引用
收藏
页码：617 / 621
页数：5
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