Improvement of the current-voltage characteristics of a tunneling dielectric by adopting a Si3N4/SiO2/Si3N4 multilayer for flash memory application -: art. no. 152106

被引:15
作者
Hong, SH
Jang, JH
Park, TJ
Jeong, DS
Kim, M
Hwang, CS
Won, JY
机构
[1] Seoul Natl Univ, Sch Mat Sci & Engn, Seoul 151742, South Korea
[2] Seoul Natl Univ, Interuniv Semicond Res Ctr, Seoul 151742, South Korea
[3] Samsung Adv Inst Technol, Analyt Engn Ctr, Suwon 440600, South Korea
关键词
D O I
10.1063/1.2093932
中图分类号
O59 [应用物理学];
学科分类号
摘要
Superior characteristics of an atomic-layer-deposited (ALD) Si3N4 layer and Si3N4/SiO2/Si3N4 stacked layers as a tunneling gate dielectric for nonvolatile flash memory application are reported. Compared to a single layer of SiO2 electric field-sensitive characteristics were obtained by barrier profile engineering with a stacked layer; a lower leakage current at a low field and a higher leakage current at a high field. The stacked dielectric layer showed Fowler-Nordheim tunneling. However, the interfacial potential barrier profile was somewhat smoothed by chemical interaction between the individual layers. The interfacial trap density of this dielectric with an ALD Si3N4 bottom layer was as low as 4x10(-10)/cm(2) eV near the mid-gap energy state, but the reoxidation process degraded the interface quality. The degradation mechanism was studied. (C) 2005 American Institute of Physics.
引用
收藏
页码:1 / 3
页数:3
相关论文
共 12 条
[1]  
Baik SJ, 2003, 2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, P545
[2]   Write/erase cycling endurance of memory cells with SiO2/HfO2 tunnel dielectric [J].
Blomme, P ;
Van Houdt, J ;
De Meyer, K .
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2004, 4 (03) :345-352
[3]  
Degraeve R, 2003, 2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, P935
[4]  
Dong-Chan Kim, 2002, International Electron Devices Meeting. Technical Digest (Cat. No.02CH37358), P919, DOI 10.1109/IEDM.2002.1175986
[5]   Ultrathin (<4 nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics:: Understanding the processing, structure, and physical and electrical limits [J].
Green, ML ;
Gusev, EP ;
Degraeve, R ;
Garfunkel, EL .
JOURNAL OF APPLIED PHYSICS, 2001, 90 (05) :2057-2121
[6]  
HORI T, 1997, GATE DIELECTRICS MOS, P101
[7]   Conductance viewed as transmission [J].
Imry, Y ;
Landauer, R .
REVIEWS OF MODERN PHYSICS, 1999, 71 (02) :S306-S312
[8]   Transport model in n++-poly/SiOx/SiO2/p-sub MOS capacitors for low-voltage nonvolatile memory applications [J].
Irrera, F ;
Marangelo, L .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2000, 47 (02) :372-377
[9]   Enhanced injection in n++-poly/SiOx/SiO2/p-sub MOS capacitors for low-voltage nonvolatile memory applications:: Experiment [J].
Irrera, F ;
Russo, F .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1999, 46 (12) :2315-2322
[10]   Layered tunnel barriers for nonvolatile memory devices [J].
Likharev, KK .
APPLIED PHYSICS LETTERS, 1998, 73 (15) :2137-2139