Low power hardware architecture for VBSME using pixel truncation

被引：3

作者：

Bahari, Asral ^{[1
]}

Arslan, Tughrul ^{[1
]}

Erdogan, Ahmet T. ^{[1
]}

机构：

[1] Univ Edinburgh, Sch Engn & Elect, Edinburgh EH8 9YL, Midlothian, Scotland

来源：

21ST INTERNATIONAL CONFERENCE ON VLSI DESIGN: HELD JOINTLY WITH THE 7TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS | 2008年

关键词：

D O I：

10.1109/VLSI.2008.100

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents an efficient architecture to implement low power variable block size motion estimation (VBSME) using full search. Power reduction is achieved by performing the search in two steps: low pixel resolution and full pixel resolution. We analysed the computation and memory units needed to support these two search modes. The proposed architecture reduces the total energy consumption by 50% with 6% additional area compared to the conventional architecture.

引用

页码：389 / 394

页数：6

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