CMP applications for sub-0.25μm process technologies

被引:0
|
作者
Pramanik, D [1 ]
Weling, M [1 ]
Lin, XW [1 ]
机构
[1] VLSI Technol Inc, San Jose, CA 95131 USA
来源
CHEMICAL MECHANICAL PLANARIZATION IN INTEGRATED CIRCUIT DEVICE MANUFACTURING | 1998年 / 98卷 / 07期
关键词
D O I
暂无
中图分类号
O646 [电化学、电解、磁化学];
学科分类号
081704 ;
摘要
This paper shows how CMP is a key enabler for sub-0.25 mu m processes - CMP can be effectively used in process architectures to form shallow trench isolation, metallize gates, form Cu-based interconnects and low "k" dielectrics. We describe the CMP challenges for these various process applications, review their current status and future trends, and suggest some novel techniques to improve their implementation.
引用
收藏
页码:1 / 8
页数:8
相关论文
共 50 条
  • [31] Sub-0.25 mu m single N+-polycide gate CMOS technology for 2.5V applications
    Ma, ZJ
    Choi, JY
    Lien, CD
    1996 54TH ANNUAL DEVICE RESEARCH CONFERENCE DIGEST, 1996, : 16 - 17
  • [32] Sub-0.25μm i-line photoresist:: The role of advanced resin technology
    Xu, CB
    Zampini, A
    Sandford, H
    Lachowski, J
    Carmody, J
    MICROLITHOGRAPHY 1999: ADVANCES IN RESIST TECHNOLOGY AND PROCESSING XVI, PTS 1 AND 2, 1999, 3678 : 739 - 750
  • [33] Implementation of a closed-loop CD and overlay controller for sub-0.25 μm patterning
    Sturtevant, J
    Weilemann, M
    Green, K
    Dwyer, J
    Robertson, E
    Hershey, R
    METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XII, 1998, 3332 : 461 - 470
  • [34] NA/sigma optimisation strategies for an advanced DUV stepper applied to 0.25 mu m and sub-0.25 mu m critical levels
    deBeeck, MO
    Ronse, K
    Ghandehari, K
    Jaenen, P
    Botermans, H
    Finders, J
    Lilygren, J
    Baker, D
    Vandenberghe, G
    DeBisschop, P
    Maenhoudt, M
    VandenHove, L
    OPTICAL MICROLITHOGRAPHY X, 1997, 3051 : 320 - 332
  • [35] Advanced gate technology for sub-0.25 micron CMOSFETs
    King, TJ
    MICROELECTRONIC DEVICE TECHNOLOGY II, 1998, 3506 : 41 - 48
  • [36] Novel co-sputtered fluorinated amorphous carbon films for sub-0.25 μm low κ damascene multilevel interconnect applications
    Zhu, W
    Pai, CS
    Bair, HE
    Krautter, HW
    Opila, RL
    Dennis, BS
    Pinczuk, A
    Chabal, YJ
    Grundmeier, G
    Graebner, JE
    Cheung, KP
    Schilling, FC
    Case, CB
    Liu, R
    Jin, S
    INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST, 1998, : 845 - 848
  • [37] Integration of multi-level copper metallization into a high performance sub-0.25μm technology
    Venkatraman, R
    Jain, A
    Farkas, J
    Mendonca, J
    Hamilton, G
    Capasso, C
    Denning, D
    Simpson, C
    Rogers, B
    Frisa, L
    Ong, TP
    Herrick, M
    Kaushik, V
    Gregory, R
    Apen, E
    Angyal, M
    Filipiak, S
    Crabtree, P
    Sparks, T
    Anderson, S
    Coronell, D
    Islam, R
    Smith, B
    Fiordalice, R
    Kawasaki, H
    Klein, J
    Venkatesan, S
    Weitzman, E
    ADVANCED INTERCONNECTS AND CONTACT MATERIALS AND PROCESSES FOR FUTURE INTEGRATED CIRCUITS, 1998, 514 : 41 - 52
  • [38] Dry development of sub-0.25 mu m features patterned with 193 nm silylation resist
    Palmateer, SC
    Forte, AR
    Kunz, RR
    Horn, MW
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY A, 1996, 14 (03): : 1132 - 1136
  • [39] Sub-0.25 mu m ultra-thin SOI CMOS with a single N+ gate process for low-voltage and low-power applications
    Raynaud, C
    Faynot, O
    Pelloie, JL
    Tedesco, S
    Ullmann, B
    Dunne, B
    Guegan, G
    Lerme, M
    1996 IEEE INTERNATIONAL SOI CONFERENCE PROCEEDINGS, 1996, : 80 - 81
  • [40] Sub-0.25 mu m optical lithography using deep-UV and optical enhancement techniques
    Vandenhove, L
    Ronse, K
    ULSI SCIENCE AND TECHNOLOGY / 1997: PROCEEDINGS OF THE SIXTH INTERNATIONAL SYMPOSIUM ON ULTRALARGE SCALE INTEGRATION SCIENCE AND TECHNOLOGY, 1997, 1997 (03): : 503 - 514