Localized Charge-Dependent Threshold Voltage Analysis of Gate-Material-Engineered Junctionless Nanowire Transistor

被引：19

作者：

Pratap, Yogesh ^{[1
]}

Haldar, Subhasis ^{[2
]}

Gupta, Radhey Shyam ^{[3
]}

Gupta, Mridula ^{[1
]}

机构：

[1] Univ Delhi, Dept Elect Sci, Semicond Device Res Lab, New Delhi 110021, India

[2] Univ Delhi, Motilal Nehru Coll, Dept Phys, New Delhi 110021, India

[3] Maharaja Agrasen Inst Technol, Dept Elect & Commun Engn, New Delhi 110086, India

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2015年 / 62卷 / 08期

关键词：

Hot-carrier effects; junctionless nanowire transistor (JNT); localized charges; temperature sensitivity; SILICON; MOSFET; MODEL; TEMPERATURE; INTEGRATION; MOBILITY; STRESS; SI;

D O I：

10.1109/TED.2015.2441777

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, the threshold voltage analysis of junctionless nanowire transistor (JNT) due to radiation/process/stress/hot-carrier damage-induced localized/fixed charges at elevated temperatures is discussed. A temperature-dependent threshold voltage model for JNT with localized charges has been developed including the source/drain depleted regions. The impact of position, density, and polarity of localized charges on channel potential, bandgap energy, and threshold voltage is studied. Four different localized charge density profiles have been used to evaluate the performance degradation. The results demonstrate that localized charges significantly change the device threshold voltage and temperature sensitivity and show less detrimental effect at elevated temperatures.

引用

页码：2598 / 2605

页数：8