Localized Charge-Dependent Threshold Voltage Analysis of Gate-Material-Engineered Junctionless Nanowire Transistor

被引:19
|
作者
Pratap, Yogesh [1 ]
Haldar, Subhasis [2 ]
Gupta, Radhey Shyam [3 ]
Gupta, Mridula [1 ]
机构
[1] Univ Delhi, Dept Elect Sci, Semicond Device Res Lab, New Delhi 110021, India
[2] Univ Delhi, Motilal Nehru Coll, Dept Phys, New Delhi 110021, India
[3] Maharaja Agrasen Inst Technol, Dept Elect & Commun Engn, New Delhi 110086, India
关键词
Hot-carrier effects; junctionless nanowire transistor (JNT); localized charges; temperature sensitivity; SILICON; MOSFET; MODEL; TEMPERATURE; INTEGRATION; MOBILITY; STRESS; SI;
D O I
10.1109/TED.2015.2441777
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, the threshold voltage analysis of junctionless nanowire transistor (JNT) due to radiation/process/stress/hot-carrier damage-induced localized/fixed charges at elevated temperatures is discussed. A temperature-dependent threshold voltage model for JNT with localized charges has been developed including the source/drain depleted regions. The impact of position, density, and polarity of localized charges on channel potential, bandgap energy, and threshold voltage is studied. Four different localized charge density profiles have been used to evaluate the performance degradation. The results demonstrate that localized charges significantly change the device threshold voltage and temperature sensitivity and show less detrimental effect at elevated temperatures.
引用
收藏
页码:2598 / 2605
页数:8
相关论文
共 50 条
  • [1] Gate-Material-Engineered Junctionless Nanowire Transistor (JNT) With Vacuum Gate Dielectric for Enhanced Hot-Carrier Reliability
    Pratap, Yogesh
    Haldar, Subhasis
    Gupta, R. S.
    Gupta, Mridula
    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2016, 16 (03) : 360 - 369
  • [2] A Junctionless Nanowire Transistor With a Dual-Material Gate
    Lou, Haijun
    Zhang, Lining
    Zhu, Yunxi
    Lin, Xinnan
    Yang, Shengqi
    He, Jin
    Chan, Mansun
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2012, 59 (07) : 1829 - 1836
  • [3] A Physics Based Approach for Threshold Voltage Modelling of Symmetric Double Gate Junctionless Transistor with Multi Material Gate
    Sarma, Kaushik Chandra Deva
    JOURNAL OF NANOELECTRONICS AND OPTOELECTRONICS, 2018, 13 (04) : 479 - 483
  • [4] A Quasi 2-D Electrostatic Potential and Threshold Voltage Model for Junctionless Triple Material Cylindrical Surrounding Gate Si Nanowire Transistor
    Manikandan, S.
    Dhanaselvam, P. Suveetha
    Pandian, M. Karthigai
    JOURNAL OF NANOELECTRONICS AND OPTOELECTRONICS, 2021, 16 (02) : 318 - 323
  • [5] Effects of uniaxial strain on gate capacitance and threshold voltage of double gate junctionless transistor
    Adnan, Md. Mohsinur Rahman
    Khosru, Quazi D. M.
    2018 IEEE 13TH NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE (NMDC), 2018, : 319 - 322
  • [6] Linearity Analysis of Gate Engineered Dopingless And Junctionless Silicon Nanowire FET
    Singh, Sarabdeep
    Raman, Ashish
    Kumar, Naveen
    Ranjan, Ravi
    Shekhar, Deep
    Anand, Sunny
    2019 6TH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND INTEGRATED NETWORKS (SPIN), 2019, : 215 - 219
  • [7] A new threshold voltage model for omega gate cylindrical nanowire transistor
    Ray, Biswajit
    Mahapatra, Santanu
    21ST INTERNATIONAL CONFERENCE ON VLSI DESIGN: HELD JOINTLY WITH THE 7TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS, 2008, : 447 - 452
  • [8] Performance Investigation of Charge Plasma Based Dual Material Gate Junctionless Transistor
    Amin, S. Intekhab
    Anand, Sunny
    Sarin, R. K.
    2016 IEEE UTTAR PRADESH SECTION INTERNATIONAL CONFERENCE ON ELECTRICAL, COMPUTER AND ELECTRONICS ENGINEERING (UPCON), 2016, : 167 - 172
  • [9] Design and Analysis of Source Engineered with High Electron Mobility Material Triple Gate Junctionless Field Effect Transistor
    Shringi, Shivangi
    Raman, Ashish
    Singh, Sarabdeep
    Kumar, Naveen
    JOURNAL OF NANOELECTRONICS AND OPTOELECTRONICS, 2019, 14 (06) : 825 - 832
  • [10] Analytical Threshold Voltage Model of Junctionless Double-Gate MOSFETs With Localized Charges
    Woo, Jong-Ho
    Choi, Ji-Min
    Choi, Yang-Kyu
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2013, 60 (09) : 2951 - 2955