Multiplier-free structures for exact generation of natural powers of integers

被引：1

作者：

Samadi, S ^{[1
]}

Ahmad, MO ^{[1
]}

Swamy, MNS ^{[1
]}

机构：

[1] Concordia Univ, Dept Elect & Comp Engn, Montreal, PQ H3G 1M8, Canada

来源：

2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS | 2005年

关键词：

D O I：

10.1109/ISCAS.2005.1464796

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

It is shown that the sequence of an arbitrary natural power of consecutive integers can be generated without any multiplications as the impulse response of a multirate recursive structure. This multistage structure has a regular configuration consisting of multirate building blocks and accumulators. A nonrecursive structure is also developed for the generation of the power sequence for a prescribed finite length. This feedforward structure consists of layers of summation nodes interconnected in a regular manner. The two types of multiplier-free discrete-time structures generate the exact values of natural kth powers of consecutive integers in a simple, regular and scalable manner.

引用

页码：1146 / 1149

页数：4

共 50 条

[41] Multiplier-free IIR filter realizations with periodically time-varying coefficients [J].

Tantaratana, S .

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 1997, 7 (04) :231-248

[42] Multiplier-free Blind Phase Noise Estimation for CO-OFDM Transmission [J].

Le, S. T. ;

Mac Suibhne, N. ;

McCarthy, M. E. ;

Ellis, A. D. ;

Turitsyn, S. K. .

ECOC 2015 41ST EUROPEAN CONFERENCE ON OPTICAL COMMUNICATION, 2015,

[43] MULTIPLIER-FREE MODULATION SCHEMES FOR PCM/FDM AND AUDIO/FDM CONVERSION. [J].

Fettweis, Alfred .

1978, 32 (12) :477-485

[44] MULTIPLIER-FREE MODULATION SCHEMES FOR PCM-FDM AND AUDIO-FDM CONVERSION [J].

FETTWEIS, A .

AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 1978, 32 (12) :477-485

[45] Design optimisation of multiplier-free parallel pipelined FFT on field programmable gate array [J].

Godi, Prasanna Kumar ;

Krishna, Battula Tirumala ;

Kotipalli, Pushpa .

IET CIRCUITS DEVICES & SYSTEMS, 2020, 14 (07) :995-1000

[46] A Low-Power Keyword Spotting Chip with Multiplier-Free MFCC Feature Extractor [J].

Yang, Jingsen .

IEICE ELECTRONICS EXPRESS, 2025,

[47] Dynamical analysis of an improved FitzHugh-Nagumo neuron model with multiplier-free implementation [J].

Quan Xu ;

Xiongjian Chen ;

Bei Chen ;

Huagan Wu ;

Ze Li ;

Han Bao .

Nonlinear Dynamics, 2023, 111 :8737-8749

[48] Fir filters with punctured radix-8 symmetric coefficients: Design and multiplier-free [J].

Boonyanant, P ;

Tantaratana, S .

CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2002, 21 (04) :345-367

[49] A Multiplier-Free Discrete Cosine Transform Architecture Using Approximate Full Adder and Subtractor [J].

Esmaeili, Elham ;

Shiri, Nabiollah ;

Rafiee, Mahmood ;

Sadeghi, Ayoub .

IEEE EMBEDDED SYSTEMS LETTERS, 2024, 16 (04) :441-444

[50] Dynamical analysis of an improved FitzHugh-Nagumo neuron model with multiplier-free implementation [J].

Xu, Quan ;

Chen, Xiongjian ;

Chen, Bei ;

Wu, Huagan ;

Li, Ze ;

Bao, Han .

NONLINEAR DYNAMICS, 2023, 111 (09) :8737-8749

← 1 2 3 4 5 →