Performance Optimization of Error Detection Based on Speculative Reconfiguration

被引：0

作者：

Lifa, Adrian Alin ^{[1
]}

Eles, Petru ^{[1
]}

Peng, Zebo ^{[1
]}

机构：

[1] Linkoping Univ, Linkoping, Sweden

来源：

PROCEEDINGS OF THE 48TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC) | 2011年

关键词：

Error detection implementation; reconfigurable systems; fault tolerance; FPGA; system-level optimization;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an approach to minimize the average program execution time by optimizing the hardware/software implementation of error detection. We leverage the advantages of partial dynamic reconfiguration of FPGAs in order to speculatively place in hardware those error detection components that will provide the highest reduction of execution time. Our optimization algorithm uses frequency information from a counter-based execution profile of the program. Starting from a control flow graph representation, we build the interval structure and the control dependence graph, which we then use to guide our error detection optimization algorithm.

引用

页码：369 / 374

页数：6

共 21 条

[1]

[Anonymous], 2005, ACM Trans. Archit. Code Optim

[2] Software and hardware techniques for SEU detection in IP processors [J].