Theory of the Junctionless Nanowire FET

被引:186
作者
Gnani, Elena [1 ,2 ]
Gnudi, Antonio [1 ,2 ]
Reggiani, Susanna [1 ,2 ]
Baccarani, Giorgio [1 ,2 ]
机构
[1] Univ Bologna, E De Castro Adv Res Ctr Elect Syst ARCES, I-40125 Bologna, Italy
[2] Univ Bologna, Dept Elect Comp Sci & Syst, I-40136 Bologna, Italy
关键词
Depletion-mode field-effect transistor (FET); junctionless field-effect transistor (JL-FET); nanowire field-effect transistor (NW-FET); subthreshold slope (SS); DOUBLE-GATE; MODEL; TRANSPORT; TRANSISTORS;
D O I
10.1109/TED.2011.2159608
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we model the electrical properties of the junctionless (JL) nanowire field-effect transistor (FET), which has been recently proposed as a possible alternative to the junction-based FET. The analytical model worked out here assumes a cylindrical geometry and is meant to provide a physical understanding of the device behavior. Most notably, it aims to clarify the motivation for its nearly ideal subthreshold slope and its excellent ON-state current while being a depletion device with lower electron mobility due to impurity scattering. At the same time, the model clarifies a constraint binding the allowable value of the doping density per unit length and its impact on the overall device performance. The device variability and the parasitic source/drain resistances are identified as the most important limitations of the JL nanowire field-effect transistor.
引用
收藏
页码:2903 / 2910
页数:8
相关论文
共 20 条
  • [1] [Anonymous], 2008, Sentaurus Device User's Manual
  • [2] Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's
    Auth, CP
    Plummer, JD
    [J]. IEEE ELECTRON DEVICE LETTERS, 1997, 18 (02) : 74 - 76
  • [3] Precise Modeling Framework for Short-Channel Double-Gate and Gate-All-Around MOSFETs
    Borli, Hakon
    Kolberg, Sigbjorn
    Fjeldly, Tor A.
    Iniguez, Benjamin
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55 (10) : 2678 - 2686
  • [4] Colinge JP, 2010, NAT NANOTECHNOL, V5, P225, DOI [10.1038/nnano.2010.15, 10.1038/NNANO.2010.15]
  • [5] A Model of the Gate Capacitance of Surrounding Gate Transistors: Comparison With Double-Gate MOSFETs
    Garcia Ruiz, Francisco J.
    Maria Tienda-Luna, Isabel
    Godoy, Andres
    Donetti, Luca
    Gamiz, Francisco
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2010, 57 (10) : 2477 - 2483
  • [6] Quasi-Ballistic Transport in Nanowire Field-Effect Transistors
    Gnani, Elena
    Gnudi, Antonio
    Reggiani, Susanna
    Baccarani, Giorgio
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55 (11) : 2918 - 2930
  • [7] Band Effects on the Transport Characteristics of Ultrascaled SNW-FETs
    Gnani, Elena
    Gnudi, Antonio
    Reggiani, Susanna
    Luisier, Mathieu
    Baccarani, Giorgio
    [J]. IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2008, 7 (06) : 700 - 709
  • [8] Explicit continuous model for long-channel undoped surrounding gate MOSFETs
    Iñíguez, B
    Jiménez, D
    Roig, J
    Hamid, HA
    Marsal, LF
    Pallarès, J
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2005, 52 (08) : 1868 - 1873
  • [9] Continuous analytic I-V model for surrounding-gate MOSFETs
    Jiménez, D
    Iñíguez, B
    Suñé, J
    Marsal, LF
    Pallarès, J
    Roig, J
    Flores, D
    [J]. IEEE ELECTRON DEVICE LETTERS, 2004, 25 (08) : 571 - 573
  • [10] Modeling of nanoscale gate-all-around MOSFETs
    Jiménez, D
    Sáenz, JJ
    Iñíguez, B
    Suñé, J
    Marsal, LF
    Pallarès, J
    [J]. IEEE ELECTRON DEVICE LETTERS, 2004, 25 (05) : 314 - 316