Output impedance design of parallel-connected UPS inverters

被引：0

作者：

Guerrero, JM ^{[1
]}

de Vicuña, LG ^{[1
]}

Matas, J ^{[1
]}

Miret, J ^{[1
]}

Castilla, M ^{[1
]}

机构：

[1] Dept Engn Sistemas Automat & Informat Ind, Barcelona 08036, Spain

来源：

PROCEEDINGS OF THE IEEE-ISIE 2004, VOLS 1 AND 2 | 2004年

关键词：

output impedance; parallel operation; uninterruptible power supplies; wireless control;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper deals with the design of the output impedance of UPS inverters with parallel-connection capability. The inner Control loops are considered in the design of the Controllers that makes possible the power sharing among the UPS modules. In these paralleled units, the power-sharing. outer control loops are based on the P/Q droop method in order to avoid any communication among the modules. The power sharing accuracy is highly sensitive to the output impedance of the inverters, making necessary the tight adjustment of this impedance. Novel control loops are proposed to achieve stable output impedance value, and, therefore, proper power balance is guarantee when sharing both linear and nonlinear loads.

引用

页码：1123 / 1128

页数：6

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