ARM7 compatible 32-bit RISC processor design and verification

被引：4

作者：

Jeong, GY ^{[1
]}

Park, JS ^{[1
]}

Jo, HW ^{[1
]}

Yoon, BW ^{[1
]}

Lee, MJ ^{[1
]}

机构：

[1] Pusan Natl Univ, Dept Elect Engn, Pusan 609735, South Korea

来源：

KORUS 2005, PROCEEDINGS | 2005年

关键词：

RISC; microprocessor; ARM7;

D O I：

10.1109/KORUS.2005.1507795

中图分类号：

F [经济];

学科分类号：

02 ;

摘要：

The design and verification of a 32-bit general-purpose microprocessor, which is compatible with ARM7 RISC core, is described. In the architectural point of view, the processor has 3-stage pipeline, 6 register banks, 32-bit ALU, and 4-cycle MAC. The core described here was designed by latch base for low power and low complexity. Its functional operation was verified by comparison the results of logic simulation with those of the commercial simulator. Each instruction and its random combinations were tested. The designed core was emulated to check its proper operation for various applications, such as ADPCM, SOLA (voice speed variation), MP3 decoding. Finally it was implemented in 0.5 mu m CMOS process and it carried out successfully those algorithms.

引用

页码：607 / 610

页数：4

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