A 99-mm2, 0.7-W, single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mbit embedded DRAM for portable 422P@HL encoder system

被引：4

作者：

Kumaki, S ^{[1
]}

Takata, H ^{[1
]}

Ajioka, Y ^{[1
]}

Ooishi, T ^{[1
]}

Ishihara, K ^{[1
]}

Hanami, A ^{[1
]}

Tsuji, T ^{[1
]}

Kanehira, Y ^{[1
]}

Watanabe, T ^{[1
]}

Morishima, C ^{[1
]}

Yoshizawa, T ^{[1
]}

Sato, H ^{[1
]}

Hattori, S ^{[1
]}

Koshio, A ^{[1
]}

Tsukamoto, K ^{[1
]}

Matsumura, T ^{[1
]}

机构：

[1] Mitsubishi Electr Corp, Syst LSI Dev Ctr, Itami, Hyogo 6648641, Japan

来源：

PROCEEDINGS OF THE IEEE 2001 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2001年

关键词：

D O I：

10.1109/CICC.2001.929815

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A scalable single-chip 422P@ML MPEG-2 video, audio, and system encoder LSI for portable 422P@HL system is described. The encoder LSI is implemented using 0.13 mum embedded DRAM technology. It integrates 3-M logic gates and 64-Mbit DRAM in an area of 99-mm(2). The power consumption is suppressed to 0.7-Watts by adopting a low power DRAM core. It performs real-time 422P@ML video encoding, audio encoding, and system encoding with no external DRAM. Furthermore, the encoder LSI realizes a 422P@HL video encoder with multi-chip configuration, due to its scalable architecture. This results in a PC-card size 422P@HL encoder with lowest power consumption for portable HDTV codec system.

引用

页码：425 / 428

页数：4

共 8 条

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