A 3.5 GHz High-efficiency CMOS RF Power Amplifier with Adaptive Bias

被引：0

作者：

Chen, Yi-Chen ^{[1
]}

Yang, Jeng-Rern ^{[1
]}

机构：

[1] Yuan Ze Univ, Dept Commun Engn, Microwave Lab, Jhong Li City 320, Taoyuan County, Taiwan

来源：

PIERS 2010 XI'AN: PROGRESS IN ELECTROMAGNETICS RESEARCH SYMPOSIUM PROCEEDINGS, VOLS 1 AND 2 | 2010年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper proposes a high-efficiency 3.5 GHz CMOS power amplifier that uses an improved linearizer as an adaptive bias control circuit. The proposed circuit is simulated by TSMC 0.18 mu m RF CMOS process. At the 1-dB compression point (P1dB), the power amplifier exhibits 25.5 dBm of output power with a high power-added-efficiency (PAE) of 39% and sufficient gain (25.5 dB) at a supply voltage of 3.3 V. At the output power 6-dB back-off from P1dB, the PAE remains at 15%. The proposed structure improves PAE by 5%similar to 6% more than the resistor bias.

引用

页码：1526 / 1529

页数：4

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