A fault tolerant approach to microprocessor design

被引:0
作者
Weaver, C [1 ]
Austin, T [1 ]
机构
[1] Univ Michigan, Dept Elect Engn & Comp Sci, Adv Comp Architecture Lab, Ann Arbor, MI 48109 USA
来源
INTERNATIONAL CONFERENCE ON DEPENDABLE SYSTEMS AND NETWORKS, PROCEEDINGS | 2001年
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We propose a fault-tolerant approach to reliable microprocessor design. Our approach, based on the use of an on-line checker component in the processor pipeline, provides significant resistance to core processor design errors and operational faults such as supply voltage noise and energetic particle strikes. We show through cycle-accurate simulation and timing analysis of a physical checker design that our approach preserves system performance while keeping area overheads and power demands low. Furthermore, analyses suggest that the checker is a fairly simple state machine that can be formally verified, scaled in performance, and reused. Further simulation analyses show virtually no performance impacts when our simple checker design is coupled with a high-performance microprocessor model. Timing analyses indicate that a fully synthesized unpipelined 4-wide checker component in 0.25um technology is capable of checking Alpha instructions at 288 MHz. Physical analyses also confirm that costs are quite modest; our prototype checker requires less than 6% the area and 1.5% the power of an Alpha 21264 processor in the some technology. Additional improvements to the checker component are described which allow for improved detection of design, fabrication and operational faults.
引用
收藏
页码:411 / 420
页数:4
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