Delay Monitoring System With Multiple Generic Monitors for Wide Voltage Range Operation

As the semiconductor process technology continuously scales down, circuit delay variations due to manufacturing and environmental variations become more and more serious. These delay variations are hardly predictable and thus require an additional design margin, which impedes the chance to reduce the area and power consumption of a chip. One of the best solutions to alleviate this problem is to measure circuit delays at run time and control the supply voltage accordingly through a closed-loop dynamic voltage and frequency scaling (DVFS) scheme. The key issue of this scheme is the delay mismatch between the monitoring circuit and the target block. A large delay mismatch might lose the advantage of the closed-loop DVFS. It becomes much worse as a circuit block operates in wider voltage range, from near-threshold voltage to super-overdrive voltage. This paper proposes novel delay monitoring systems with multiple generic monitors for wide voltage range operation, which provide a better delay correlation between the monitoring circuit and the target block compared to conventional monitoring approaches. The proposed approaches reduce the maximum error by up to 91% for a popular processor core in a 14-nm FinFET process technology, thereby bring a decrease of design margin, lower-power, and/or lower-cost design.