共 15 条
- [1] [Anonymous], 1986, FAULT TOLERANT COMPU
- [2] Fault analysis for networks with concurrent error detection [J]. IEEE DESIGN & TEST OF COMPUTERS, 1998, 15 (04): : 66 - 74
- [3] Bolchini C, 1997, SECOND ANNUAL IEEE INTERNATIONAL CONFERENCE ON INNOVATIVE SYSTEMS IN SILICON, 1997 PROCEEDINGS, P196, DOI 10.1109/ICISS.1997.630260
- [4] Bolchini C, 1997, ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV, P2741, DOI 10.1109/ISCAS.1997.612892
- [6] DE K, 1994, IEEE T VLSI SYST, V2, P189
- [7] On the design of self-checking functional units based on Shannon circuits [J]. DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION 1999, PROCEEDINGS, 1999, : 368 - 375
- [8] KAKAROUNTAS AP, 2002, P IEEE S CIRC SYSTEM, V4, P313
- [9] Lo J.-C., 1993, Proceedings. The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (Cat. No.93TH0571-0), P263, DOI 10.1109/DFTVS.1993.595821