An efficient VLSI architecture of a Layered Space-Time receiver

This paper presents a practical implementation of a Layered Space-Time (LST) receiver targeting a Xilinx Virtex-II FPGA. The architecture is based on multipass burst processing, and includes burst buffers for each antenna, channel parameter estimation modules exploiting a training sequence, and a simple matrix inversion adaptation mechanism. LST architectures involve significant implementation complexity and various refinements have been proposed in the literature to mitigate this aspect. Our receiver is based on novel modifications to the standard LST algorithm which enable unprecedented implementation simplicity, avoiding complex operations such as divisions and square roots, while suffering a negligible BER degradation.