Below 45nm Low-k Layer Stress Minimization Guide for High-Performance Flip-Chip Packages with Copper Pillar Bumping

In this paper, the FEM based various parametric studies such as packaging material and structural effects, under bump metallization and passivation structures and material property effects on the low k layer are investigated for the flip-chip packaging with Cu pillar interconnection. The results showed that the stress of the low k layer is directly concerned wirh the CTE mismatch between low k die and substrate constrained by Cu pillar and maximized at the bump near the die corner after flip chip attach process before underfill. The stress contour shows that the low k area is affected by both tensile stress and compressive stress. The experimentally inspected low k damaged area showed half moon shape which reveals the failure mode is closely related with the tensile stress near the Al to Cu pillar interface. The comparison results show that the Cu pillar has 20% higher stress than lead free solder and 40% than eutectic solder case. The structural DOE shows that the reducing flip-chip die and substrate thickness and also reducing passivation opening cases showed effective for reducing low k stress after flip chip attach. After underfill and mold or MUF only process, stress change of low k layer showed good agreement to the CTE variation of underfill or MUF which means thermal expansion of underfill / MUF is governing factor for low k stress for the after assembly. Compared with CUF, MUF which has lower CTE than CUF showed relatively lower stress on the low k layer. By applying optimized structure and material properties of package, UBM and passivation layers, the stress of the low k layer can be reduced to the relatively safe level where the stress is lower than the eutectic solder applied case of the reference structure.