Observation Point Insertion Using Deep Learning

被引:0
作者
Bhaskaran, Bonita [1 ]
Banerjee, Sanmitra [1 ]
Narayanun, Kaushik [1 ]
Hung, Shao-Chun [2 ]
Mojaveri, Seyed Nima Mozaffari [1 ]
Liu, Mengyun [1 ]
Chen, Gang [1 ]
Liang, Tung-Che [1 ]
机构
[1] NVIDIA Corp, DFX Engn, Santa Clara, CA 95051 USA
[2] Duke Univ, Durham, NC USA
来源
2022 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, ICCAD | 2022年
关键词
Observation point; ATPG; pattern count; deep learning; graph convolutional networks;
D O I
10.1145/3508352.3561122
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Silent Data Corruption (SDC) is one of the critical problems in the field of testing, where errors or corruption do not manifest externally. As a result, there is increased focus on improving the outgoing quality of dies by striving for better correlation between structural and functional patterns to achieve a low DPPM. This is very important for NVIDIA's chips due to the various markets we target; for example, automotive and data center markets have stringent in-field testing requirements. One aspect of these efforts is to also target better testability while incurring lower test cost. Since structural testing is faster than functional tests, it is important to make these structural test patterns as effective as possible and free of test escapes. However, with the rising cell count in today's digital circuits, it is becoming increasingly difficult to sensitize faults and propagate the fault effects to scanflops or primary outputs. Hence, methods to insert observation points to facilitate the detection of hard-to-detect (HtD) faults are being increasingly explored. In this work, we propose an Observation Point Insertion (OPI) scheme using deep learning with the motivation of achieving - 1) better quality test points than commercial EDA tools leading to a potential lower pattern count 2) faster turnaround time to generate the test points. In order to achieve better pattern compaction than commercial EDA tools, we employ Graph Convolutional Networks (GCNs) to learn the topology of logic circuits along with the features that influence its testability. The graph structures are subsequently used to train two GCN-type deep learning models - the first model predicts signal probabilities at different nets and the second model uses these signal probabilities along with other features to predict the reduction in test-pattern count when OPs are inserted at different locations in the design. The features we consider include structural features like gate type, gate logic, reconvergent-fanouts and testability features like SCOAP. Our simulation results indicate that the proposed machine learning models can predict the probabilistic testability metrics with reasonable accuracy and can identify observation points that reduce pattern count.
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页数:8
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