GenSeq plus : A Scalable High-Performance Accelerator for Genome Sequencing

被引:1
作者
Wang, Chao [1 ]
Gong, Lei [2 ]
Lei, Shiming [2 ]
Fang, Haijie [2 ]
Li, Xi [1 ]
Wang, Aili [1 ]
Zhou, Xuehai [1 ]
机构
[1] Univ Sci & Technol China, Hefei 230027, Anhui, Peoples R China
[2] Univ Sci & Technol China, Suzhou Inst Adv Study, Suzhou 215123, Jiangsu, Peoples R China
关键词
Pattern matching; Sequential analysis; Field programmable gate arrays; Graphics processing units; Acceleration; Hardware; Bioinformatics; Accelerator; FPGA; gene sequencing; KMP; FPGA; ARCHITECTURE;
D O I
10.1109/TCBB.2019.2947059
中图分类号
Q5 [生物化学];
学科分类号
071010 ; 081704 ;
摘要
Genome sequencing is one of the most challenging problems in computational biology and bioinformatics. As a traditional algorithm, the string match meets a challenge with the development of the massive volume of data because of gene sequencing. Surveys show that there will be a huge amount of short read segments during the process of gene sequencing and the need for a highly efficient is urgent. As a classic fast and exact single pattern matching algorithm, Knuth-Morris-Pratt (KMP) algorithm has been demonstrated in network security and computational biology. However, with the increasing amount of data in the modern society, it becomes increasingly important and essential to provide a High-performance implementation of KMP algorithm. In this article, we implement a scalable KMP accelerator based on FPGA, named GeneKMP. The accelerator is composed of different computing units to achieve a pipelined organization for higher throughput with satisfying scalability. A novel programming model is provided to alleviate the burden of the high-level programmers. We provide a greedy-based partitioning algorithm for the software/hardware design paradigms. Experimental results on the state-of-the-art Xilinx FPGA hardware prototype show that our accelerator can achieve up to a promising speedup with insignificant hardware cost and power consumption.
引用
收藏
页码:1512 / 1523
页数:12
相关论文
共 34 条
[1]   A Hardware-Efficent Multi-character String Matching Architecture Using Brute-force Algorithm [J].
Ahn, Seongyong ;
Hong, Hyejong ;
Kim, Hyunjin ;
Ahn, Jin-Ho ;
Baek, Dongmyong ;
Kang, Sungho .
2009 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2009), 2009, :464-+
[2]  
[Anonymous], 2014, INT J COMPUT APPL
[3]   A View of Cloud Computing [J].
Armbrust, Michael ;
Fox, Armando ;
Griffith, Rean ;
Joseph, Anthony D. ;
Katz, Randy ;
Konwinski, Andy ;
Lee, Gunho ;
Patterson, David ;
Rabkin, Ariel ;
Stoica, Ion ;
Zaharia, Matei .
COMMUNICATIONS OF THE ACM, 2010, 53 (04) :50-58
[4]  
Baker Zachary K., 2005, 2005 Symposium on Architectures for Networking and Communications Systems (ANCS), P193, DOI 10.1109/ANCS.2005.4675279
[5]  
Baker ZK, 2004, LECT NOTES COMPUT SC, V3203, P311
[6]   FPGA architectural research: A survey [J].
Brown, S .
IEEE DESIGN & TEST OF COMPUTERS, 1996, 13 (04) :9-15
[7]  
Chao Wang, 2011, 2011 IEEE 9th International Symposium on Parallel and Distributed Processing with Applications (ISPA), P107, DOI 10.1109/ISPA.2011.40
[8]   Accelerating the Next Generation Long Read Mapping with the FPGA-Based System [J].
Chen, Peng ;
Wang, Chao ;
Li, Xi ;
Zhou, Xuehai .
IEEE-ACM TRANSACTIONS ON COMPUTATIONAL BIOLOGY AND BIOINFORMATICS, 2014, 11 (05) :840-852
[9]  
Cho YH, 2002, LECT NOTES COMPUT SC, V2438, P452
[10]  
Dharmapurikar S, 2003, HOT INTERCONNECTS 11, P44