共 50 条
- [31] FPGA Implementation of Nonbinary Quasi-Cyclic LDPC Decoder Based On EMS Algorithm 2009 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLUMES I & II: COMMUNICATIONS, NETWORKS AND SIGNAL PROCESSING, VOL I/ELECTRONIC DEVICES, CIRUITS AND SYSTEMS, VOL II, 2009, : 1061 - 1065
- [32] A bit-serial approximate min-sum LDPC decoder and FPGA implementation 2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, 2006, : 149 - +
- [33] Efficient DSP implementation of an LDPC decoder 2004 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOL IV, PROCEEDINGS: AUDIO AND ELECTROACOUSTICS SIGNAL PROCESSING FOR COMMUNICATIONS, 2004, : 665 - 668
- [34] Efficient implementation technique of LDPC decoder ELECTRONICS LETTERS, 2001, 37 (20) : 1231 - 1232
- [35] Implementation of Sphere Decoder with Early Termination using FPGA 2013 INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND COMMUNICATION (ICSC), 2013, : 4 - 8
- [36] A 170 Mbps (8176,7156) quasi-cyclic LDPC decoder implementation with FPGA 2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, 2006, : 5095 - +
- [37] Fully parallel FPGA decoder for irregular LDPC codes 2015 23RD TELECOMMUNICATIONS FORUM TELFOR (TELFOR), 2015, : 309 - 312
- [38] From multicore LDPC decoder implementations to FPGA decoder architectures: a case study 2018 25TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 2018, : 93 - 96
- [39] IMPLEMENTATION OF A LOW POWER LDPC DECODER USING BIT SERIAL ARCHITECTURE 2014 INTERNATIONAL CONFERENCE ON INFORMATION COMMUNICATION AND EMBEDDED SYSTEMS (ICICES), 2014,
- [40] Implementation of an LDPC decoder on a vector signal processor CONFERENCE RECORD OF THE THIRTY-EIGHTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS, VOLS 1 AND 2, 2004, : 549 - 553