Area-efficient HEVC IDCT/IDST architecture for 8K x 4K video decoding

High Efficiency Video Coding (HEVC) is the newest video coding standard beyond H.264/AVC. To more efficiently compress image frames, variable block size DCT/IDCT (from 4 x 4 to 32 x 32) as well as 4 x 4 DST/IDST is employed by HEVC. In this paper, a novel area-efficient IDCT/IDST architecture for Ultra-High Definition (UHD) video applications is proposed. To reduce hardware cost and improve throughput efficiency, a novel resource sharing scheme, a template-based constant multiplication structure and a transpose buffer structure are adopted. Experimental results show that the proposed architecture can address 8K x 4K (7680 x 4320, 30 fps) video sequences at 390MHz with at least a 39.5% gate count savings. Consequently, the proposed architecture offers a cost-efficient solution for future UHD applications.