A self-calibrated delay-locked loop with low static phase error

In conventional delay-locked loop circuits, the charge and discharge of the charge pump result in mismatched current reflecting the size of the static phase error. The static phase error between feedback clock and reference clock is likely to be within tens or hundreds of picoseconds (ps). We thus propose an approach using digital calibration methods to reduce the charge pump current mismatch by means of the setup time of the D-type flip flop. The setup time of D-type flip flop is determined and duplicated to detect the phase error between the reference clock and feedback clock. It results in a very small static phase error between the reference clock and feedback clock. This paper used a 0.18 mu m CMOS process design, with a reference frequency of 700 similar to 900MHz. The active area is 0.031mm(2), and the phase error after correction is less than 5ps. Copyright (c) 2015 John Wiley & Sons, Ltd.