A new high speed and low power decoder/encoder for Radix-4 Booth multiplier

The proposed booth decoder/encoder unit is an ultrahigh-speed unit among the reported ones which was designed by modifying and creating a new format truth table with 0.18 mu m CMOS technology. According to the modified truth table, four cases are defined, and a proper circuit for each case is designed. The proposed structure is discussed considering the possible problems such as the swing and discharge problems. The gate-level delay of the proposed structure and other related works have been calculated and are compared. The propagation delay of the proposed structure has been calculated and simulated to validate the data. To justify the comparisons, other related works have been simulated again with the same condition. The propagation delay of the proposed structure is 226 ps, which is minimum compared to previous related works. The proposed structure reduces the delay by 30-200% comparing related works and also improves the delay of the multiplier 4-21%. The power consumption and the area of the structure are 477 mu w and 20 x 18 mu m(2), respectively. In this paper, Hspice software for simulating, MATLAB for numerical calculations, and Cadence for designing the layout of the proposed structure have been used.