Reliability-Aware Scheduling on Heterogeneous Multicore Processors

被引:23
|
作者
Naithani, Ajeya [1 ]
Eyerman, Stijn [2 ]
Eeckhout, Lieven [1 ]
机构
[1] Univ Ghent, Ghent, Belgium
[2] Intel, Brussels, Belgium
来源
2017 23RD IEEE INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA) | 2017年
基金
欧洲研究理事会;
关键词
VULNERABILITY FACTORS; CORES;
D O I
10.1109/HPCA.2017.12
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Reliability to soft errors is an increasingly important issue as technology continues to shrink. In this paper, we show that applications exhibit different reliability characteristics on big, high-performance cores versus small, power-efficient cores, and that there is significant opportunity to improve system reliability through reliability-aware scheduling on heterogeneous multicore processors. We monitor the reliability characteristics of all running applications, and dynamically schedule applications to the different core types in a heterogeneous multicore to maximize system reliability. Reliabilityaware scheduling improves reliability by 25.4% on average (and up to 60.2%) compared to performance-optimized scheduling on a heterogeneous multicore processor with two big cores and two small cores, while degrading performance by 6.3% only. We also introduce a novel system-level reliability metric for multiprogram workloads on (heterogeneous) multicores. We further show that our reliability-aware scheduler is robust across core count, number of big and small cores, and their frequency settings. The hardware cost in support of our reliability-aware scheduler is limited to 296 bytes per core.
引用
收藏
页码:397 / 408
页数:12
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