Reliability-Aware Scheduling on Heterogeneous Multicore Processors

被引:23
作者
Naithani, Ajeya [1 ]
Eyerman, Stijn [2 ]
Eeckhout, Lieven [1 ]
机构
[1] Univ Ghent, Ghent, Belgium
[2] Intel, Brussels, Belgium
来源
2017 23RD IEEE INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA) | 2017年
基金
欧洲研究理事会;
关键词
VULNERABILITY FACTORS; CORES;
D O I
10.1109/HPCA.2017.12
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Reliability to soft errors is an increasingly important issue as technology continues to shrink. In this paper, we show that applications exhibit different reliability characteristics on big, high-performance cores versus small, power-efficient cores, and that there is significant opportunity to improve system reliability through reliability-aware scheduling on heterogeneous multicore processors. We monitor the reliability characteristics of all running applications, and dynamically schedule applications to the different core types in a heterogeneous multicore to maximize system reliability. Reliabilityaware scheduling improves reliability by 25.4% on average (and up to 60.2%) compared to performance-optimized scheduling on a heterogeneous multicore processor with two big cores and two small cores, while degrading performance by 6.3% only. We also introduce a novel system-level reliability metric for multiprogram workloads on (heterogeneous) multicores. We further show that our reliability-aware scheduler is robust across core count, number of big and small cores, and their frequency settings. The hardware cost in support of our reliability-aware scheduler is limited to 296 bytes per core.
引用
收藏
页码:397 / 408
页数:12
相关论文
共 30 条
[1]   Radiation-induced soft errors in advanced semiconductor technologies [J].
Baumann, RC .
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2005, 5 (03) :305-316
[2]   Computing architectural vulnerability factors for address-based structures [J].
Biswas, A ;
Racunas, P ;
Cheveresan, R ;
Emer, J ;
Mukherjee, SS ;
Rangan, R .
32ND INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, PROCEEDINGS, 2005, :532-543
[3]   Upset hardened memory design for submicron CMOS technology [J].
Calin, T ;
Nicolaidis, M ;
Velazco, R .
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1996, 43 (06) :2874-2878
[4]   An Evaluation of High-Level Mechanistic Core Models [J].
Carlson, Trevor E. ;
Heirman, Wim ;
Eyerman, Stijn ;
Hur, Ibrahim ;
Eeckhout, Lieven .
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 2014, 11 (03) :127-151
[5]  
Chen JA, 2009, DES AUT CON, P927
[6]  
Chitlur Nagabhushan., 2012, HIGH PERFORMANCE COM, P1
[7]  
Duan LD, 2009, INT S HIGH PERF COMP, P129, DOI 10.1109/HPCA.2009.4798244
[8]   System-level performance metrics for multiprogram workloads [J].
Eyerman, Stijn ;
Eeckhout, Lieven .
IEEE MICRO, 2008, 28 (03) :42-53
[9]  
Greenhalgh Peter., 2011, BIGLITTLE PROCESSING
[10]  
Koufaty D, 2010, EUROSYS'10: PROCEEDINGS OF THE EUROSYS 2010 CONFERENCE, P125