Design of pipelined mixed-signal fuzzy logic controller with linguistic hedge modifiers

被引：0

作者：

Chen, CY ^{[1
]}

Hsieh, YT ^{[1
]}

Liu, BD ^{[1
]}

机构：

[1] Natl Cheng Kung Univ, Dept Elect Engn, Tainan 70101, Taiwan

来源：

2000 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS: ELECTRONIC COMMUNICATION SYSTEMS | 2000年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

In this paper, we realize the linguistic hedge fuzzy logic controller in a mixed-signal VLSI design with pipelined clocking strategy. Current-mode approach is adopted in designing the signal processing portions to simplify the circuit complexity; digital circuits are adopted to implement the programmable units. All the designs are performed with HSPICE simulation in level 28 model for a 0.35 mum SPQM CMOS process. The pipelined strategy speeds up the inference operation to 0.5M FLIPS. The supply voltage of this system is 3.3V.

引用

页码：148 / 151

页数：2

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