HoneyComb: A Multi-grained Dynamically Reconfigurable Runtime Adaptive Hardware Architecture

被引：0

作者：

Thomas, Alexander ^{[1
]}

Rueckauer, Michael ^{[1
]}

Becker, Juergen ^{[1
]}

机构：

[1] Karlsruher Inst Technol KIT, Inst Tech Informationsverarbeitung, Karlsruhe, Germany

来源：

2011 IEEE INTERNATIONAL SOC CONFERENCE (SOCC) | 2011年

关键词：

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Reconfigurable computing is a promising concept for data processing. Higher parallel utilization of the given hardware resources results in better performance and lower power consumption compared to conventional approaches like von Neumann or Harvard architectures. Nevertheless, current reconfigurable solutions have their limitations and require more scientific attention. This contribution presents a new reconfigurable architecture which targets many weaknesses like array utilization, reusability and post-compile flexibility. Therefore, new features like runtime routing, multi-grained data types, partial reconfiguration and application tailored adaptability have been implemented and tightly coupled to software tools and programming languages. A demonstration chip using TSMC 90nm standard cell technology has been designed and is currently in production.

引用

页码：335 / 340

页数：6

共 50 条

[31] A hardware/software reconfigurable architecture for adaptive wireless image communication
Panigrahi, D
Taylor, CN
Dey, S
ASP-DAC/VLSI DESIGN 2002: 7TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE AND 15TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2002, : 553 - 558
[32] Variability Mapping at Runtime Using the PAnDA Multi-reconfigurable Architecture
Bale, Simon J.
Walker, James A.
Trefzer, Martin A.
Tyrrell, Andy M.
2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2017, : 41 - 42
[33] Dynamically Compressible Context Architecture for Low Power Coarse-Grained Reconfigurable Array
Kim, Yoonjin
Mahapatra, Rabi N.
2007 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, VOLS, 1 AND 2, 2007, : 395 - 400
[34] Dynamically reconfigurable hardware-software architecture for partitioning networking functions on the SoC platform
Kim, Youngmann
Park, E. K.
Tak, Sungwoo
JOURNAL OF SYSTEMS AND SOFTWARE, 2009, 82 (10) : 1588 - 1599
[35] A Novel Loop Adaptive Hardware Design for Coarse-Grained Reconfigurable Array
Ge, Wei
Wen, Wen
Qi, Zhi
PROCEEDINGS OF THE 2013 FOURTH INTERNATIONAL CONFERENCE ON INTELLIGENT CONTROL AND INFORMATION PROCESSING (ICICIP), 2013, : 518 - 522
[36] mRTS: Run-Time System for Reconfigurable Processors with Multi-Grained Instruction-Set Extensions
Ahmed, Waheed
Shafique, Muhammad
Bauer, Lars
Henkel, Joerg
2011 DESIGN, AUTOMATION & TEST IN EUROPE (DATE), 2011, : 1554 - 1559
[37] An Evolutionary Approach to Runtime Variability Mapping and Mitigation on a Multi-Reconfigurable Architecture
Bale, Simon J.
Campos, Pedro B.
Trefzer, Martin A.
Walker, James A.
Tyrrell, Andy M.
PROCEEDINGS OF THE 2017 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2017, : 1570 - 1575
[38] A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding
Lapotre, Vianney
Murugappa, Purushotham
Gogniat, Guy
Baghdadi, Amer
Huebner, Michael
Diguet, Jean-Philippe
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 24 (01) : 383 - 387
[39] Dynamically Reconfigurable Architecture for Multi-Rate Compatible Regular LDPC Decoding
Nagashima, Akiyuki
Imai, Yuta
Togawa, Nozomu
Yanagisawa, Masao
Ohtsuki, Tatsuo
2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4, 2008, : 705 - 708
[40] HIGH-THROUGHPUT INTERPOLATION HARDWARE ARCHITECTURE WITH COARSE-GRAINED RECONFIGURABLE DATAPATHS FOR HEVC
Diniz, Claudio Machado
Shafique, Muhammad
Bampi, Sergio
Henkel, Joerg
2013 20TH IEEE INTERNATIONAL CONFERENCE ON IMAGE PROCESSING (ICIP 2013), 2013, : 2091 - 2095

← 1 2 3 4 5 →