VHDL Implementation of a Flexible and Synthesizable FFT Processor

被引：2

作者：

Correa, I. S. ^{[1
]}

Freitas, L. C.

Klautau, A.

Costa, J. C. W. A. ^{[1
]}

机构：

[1] Fed Univ Para UFPA, Dept Elect & Comp Engn, Belem, Para, Brazil

来源：

IEEE LATIN AMERICA TRANSACTIONS | 2012年 / 10卷 / 01期

关键词：

VHDL language; digital hardware design; FFT;

D O I：

10.1109/TLA.2012.6142457

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents the current stage of development of a fast Fourier transform (FFT) processor in VHDL. This processor uses fixed-point as numeric representation, taking advantage of the facilities provided by the IEEE fixed point package. Its main advantages is that it is being developed as fully parameterizable processor, in a way that the number of bits, fixed point position and number of points computed in the FFT can be easily changed. It is also able to be used in several applications such as classification algorithms and communications systems. An open source prototype core has been developed and it can perform a complete FFT transform using radix-2 with decimation in time. Results and details of this implementation are presented.

引用

页码：1180 / 1183

页数：4

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