A parameterizable HandelC divider generator for FPGAs with embedded hardware multipliers

被引：4

作者：

Hopf, J ^{[1
]}

机构：

[1] Univ S Australia, Adv Comp Res Ctr, Mawson Lakes, SA 5095, Australia

来源：

2004 IEEE INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY, PROCEEDINGS | 2004年

关键词：

D O I：

10.1109/FPT.2004.1393298

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a parameterizable tool that generates HandelC code to perform fast division on FPGAs. With the introduction of VirtexII family FPGAs, fast division is now achievable by exploiting 18-bit hardware multipliers and fast Block RAM (BRAM). Look Up Tables (LUTs) are used to store reciprocals of the denominators that are used in conjunction with the multiplier. This produces a low latency divider that consumes very little FPGA area, but at the cost of precision. In image processing applications, these properties are ideal.

引用

页码：355 / 358

页数：4