Exploiting Lithography Limits for Hardware Security Applications

被引:0
|
作者
Khan, Raihan Sayeed [1 ]
Noor, Nafisa [1 ]
Jin, Chenglu [1 ]
Muneer, Sadid [1 ]
Dirisaglik, Faruk [1 ,2 ]
Cywar, Adam [1 ]
Phuong Ha Nguyen [1 ]
van Dijk, Marten [1 ]
Gokirmak, Ali [1 ]
Silva, Helena [1 ]
机构
[1] Univ Connecticut, Dept Elect & Comp Engn, Storrs, CT 06269 USA
[2] Eskisehir Osmangazi Univ, Dept Elect & Elect Engn, TR-26480 Eskisehir, Turkey
来源
2019 IEEE 19TH INTERNATIONAL CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO 2019) | 2019年
关键词
D O I
10.1109/nano46743.2019.8993902
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Hardware security primitives such as physical obfuscated keys (POKs) allow tamper-resistant storage of random keys based on manufacturing or physical variability. The output bits of existing POK designs need to be first corrected due to measurement noise using error correction methods and then de-correlated by privacy amplification processes. These additional requirements increase the hardware overhead and reduce the efficiency of the system. In this work, we propose an intrinsically reliable POK design capable of generating random bits by exploiting the limits of the lithographic process for a given technology. Our design does not require any error correction and requires only XOR circuits for privacy amplification which reduces the hardware overhead of the whole system.
引用
收藏
页码:9 / 12
页数:4
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