A systematic error model of high-resolution pipelined analog-to-digital converters

被引：0

作者：

Chen, Tingqian ^{[1
]}

Yao, Bingkun ^{[1
]}

Xu, Jun ^{[1
]}

Ren, Junyan ^{[1
]}

机构：

[1] Fudan Univ, Dept Microelect, ASIC & Syst State Key Lab, Shanghai 200433, Peoples R China

来源：

IEEE MWSCAS'06: PROCEEDINGS OF THE 2006 49TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II | 2006年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work presents a systematic error model of high-resolution pipelined analog-to-digital converters (ADCs) implemented in MATLAB. Many errors limit linearity or noise performance of high-resolution ADCs, such as sampling distortion, slew-rate (SR) limiting, closed-loop gain variation of amplifiers, capacitor mismatch, clock jitter and thermal noise. All errors mentioned above are analyzed and modeled in a set of explicit mathematic expressions. Simulation results based on this model are compared with measured results of a 10-bit prototype ADC.

引用

页码：158 / +

页数：2

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