Effect Of Body Bias and Temperature On Snapback For a SOI-LDMOS Transistor

被引:0
作者
Sahoo, Jagamohan [1 ]
Mahapatra, Rajat [1 ]
Bhattacharyya, Amalendu Bhusan
机构
[1] Natl Inst Technol Durgapur, Dept Elect & Commun Engn, Nano Device Lab, Durgapur 713209, India
来源
2018 INTERNATIONAL SYMPOSIUM ON DEVICES, CIRCUITS AND SYSTEMS (ISDCS) | 2018年
关键词
Silicon On Insulator Lateral Diffused MOS (SOI-LDMOS); Impact Ionization (II); Parasitic Bipolar transistor; Snapback (SB) effect; Electron -Hole pair (EHP); VOLTAGE; RESISTANCE; MODEL;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper we have addressed the effect of body bias (both forward and reverse bias) and temperature on snapback voltage in a Silicon On Insulator Lateral Diffused MOS (SOI-LDMOS) transistor for the first time. Controlled simulation experiments have been carried out on a representative LDMOS structure to develop physical insight regarding the effect of body bias on the device characteristics. For temperature effect, only the temperature dependence of IDS-VDS characteristics has been presented. The simulation results are expected to be useful for developing analytical model capable of including bias and temperature dependences and validating prevailing models. The forward body bias assists the parasitic bipolar transistor to turn on in lower drain to source voltage and reduces snapback voltage from similar to 50V to similar to 20V for the dimension and parameters given in Table 1. However, the snapback voltage is increased slowly in reverse body bias. Depending on application, optimum snapback voltage may be tuned by varying the body bias. The snapback voltage hardly changed with the temperature variation from 25 degrees C to 125 degrees C.
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页数:5
相关论文
共 14 条
  • [1] A. surface-potential-based high-voltage compact LDMOS transistor model
    Aarts, A
    D'Halleweyn, N
    van Langevelde, R
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2005, 52 (05) : 999 - 1007
  • [2] Amerasekera A, 1996, 1996 IEEE INTERNATIONAL RELIABILITY PHYSICS PROCEEDINGS, 34TH ANNUAL, P318, DOI 10.1109/RELPHY.1996.492137
  • [3] [Anonymous], 2016, ATL US MAN DEV SIM S
  • [4] Appels J A., 1979, 1979 International Electron Devices Meeting, P238, DOI [DOI 10.1109/IEDM.1979.189589, 10.1109/IEDM.1979.18958946, DOI 10.1109/IEDM.1979.18958946]
  • [5] A method for the prediction of hot-carrier lifetime in floating SOI NMOSFET's
    Maeda, S
    Yamaguchi, Y
    Kim, IJ
    Joachim, HO
    Inoue, Y
    Miyoshi, H
    Yasuoka, A
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1997, 44 (12) : 2200 - 2206
  • [6] Substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel SOI MOSFET's
    Maeda, S
    Hirano, Y
    Yamaguchi, Y
    Iwamatsu, T
    Ipposhi, T
    Ueda, K
    Mashiko, K
    Maegawa, S
    Abe, H
    Nishimura, T
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1999, 46 (01) : 151 - 158
  • [7] Analysis and Modeling of the Snapback Voltage for Varying Buried Oxide Thickness in SOI-LDMOS Transistors
    Nikhil, KrishnanNadar Savithry
    DasGupta, Nandita
    DasGupta, Amitava
    Chakravorty, Anjan
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63 (10) : 4003 - 4010
  • [8] Modeling of SOI-LDMOS Transistor Including Impact Ionization, Snapback, and Self-Heating
    Radhakrishna, Ujwal
    DasGupta, Amitava
    DasGupta, Nandita
    Chakravorty, Anjan
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2011, 58 (11) : 4035 - 4041
  • [9] A PHYSICAL CHARGE-BASED MODEL FOR NON-FULLY DEPLETED SOI MOSFETS AND ITS USE IN ASSESSING FLOATING-BODY EFFECTS IN SOI CMOS CIRCUITS
    SUH, D
    FOSSUM, JG
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1995, 42 (04) : 728 - 737
  • [10] MODELING OF THE ON-RESISTANCE OF LDMOS, VDMOS, AND VMOS POWER TRANSISTORS
    SUN, SC
    PLUMMER, JD
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1980, 27 (02) : 356 - 367