An area-time-efficient residue-to-binary converter

被引：0

作者：

Wang, W ^{[1
]}

Swamy, MNS ^{[1
]}

Ahmad, MO ^{[1
]}

机构：

[1] Concordia Univ, Dept Elect & Comp Engn, Ctr Commun & Signal Proc, Montreal, PQ H3G 1M8, Canada

来源：

PROCEEDINGS OF THE 43RD IEEE MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III | 2000年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a new residue-to-binary conversion algorithm, that reduces the size of modulo operation required by Chinese remainder theorem, is introduced. Based on this algorithm, an efficient residue-to-binary converter is proposed for a general residue number system. The proposed converter achieves a significantly better performance in terms of area, time, and power consumption than those of the existing ones. For the case of the 28-bit dynamic range, the proposed converter is about 20% faster while requiring only 70% of the area, compared to the best existing converter [6]. Also, the power consumption is reduced by 16% in high speed situation and 50% in low voltage situation.

引用

页码：904 / 907

页数：4

共 10 条

[1] Bhardwaj M, 1998, INT CONF ACOUST SPEE, P3017, DOI 10.1109/ICASSP.1998.678161
[2] FAST AND FLEXIBLE ARCHITECTURES FOR RNS ARITHMETIC DECODING
ELLEITHY, KM
BAYOUMI, MA
[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1992, 39 (04): : 226 - 235
[3] Knuth E.D., 1981, ART COMPUTER PROGRAM, V2
[4] Perumal S., 1994, Proceedings. Seventh Annual IEEE International ASIC Conference and Exhibit (Cat. No.94TH0685-8), P454, DOI 10.1109/ASIC.1994.404521
[5] Skavantzos A., 1999, P IEEE INT S CIRC SY
[6] Soderstrand A., 1986, RESIDUE NUMBER SYSTE
[7] Area-time-efficient VLSI residue-to-binary converters
Srikanthan, T
Bhardwaj, M
Clarke, CT
[J]. IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 1998, 145 (03): : 229 - 235
[8] Szabo N.S., 1967, RESIDUE ARITHMETIC I
[9] TOYOSHIMA H, 1996, P IEEE INT S CIRC SY, V2, P265
[10] WANG Y, 1998, P AS C US NOV

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