A Parallel VLSI Architecture for Fast Min Max Predicate Based Region Growing Algorithm

Region Growing Segmentation is a popular segmentation scheme used for real time computer vision applications. All the implementation proposed so far lacks processing speed due to their semi parallel region grow from seed pixels. In this paper we have proposed a fully parallel merging based architecture for region growing. Beside less memory requirement for storing individual labels, the main advantage of this algorithm is its parallel local operations suitable for VLSI cell network based implementation. We have merged two neighboring pixels which have least mutual intensity differences and assigned a dual predicate to each merging pixel. The predicate is selected as minimum and maximum values of two candidate pixels. We have shown in this paper that, execution speed wise our architecture over-performs the contemporary architectures for region growing available in literature without compromising segmentation quality. Also the resource utilization is quite small due to its simple state machine based implementation.