Conducting barriers for vertical integration of ferroelectric capacitors on Si

被引:19
作者
Aggarwal, S [1 ]
Dhote, AM
Li, H
Ankem, S
Ramesh, R
机构
[1] Univ Maryland, Dept Mat & Nucl Engn, College Pk, MD 20742 USA
[2] Univ Maryland, Ctr Superconduct Res, College Pk, MD 20742 USA
关键词
D O I
10.1063/1.123301
中图分类号
O59 [应用物理学];
学科分类号
摘要
One of the issues impeding the commercialization of nonvolatile ferroelectric memories is the identification and development of a conducting diffusion barrier for the vertical integration of ferroelectric capacitors on Si-based transistors. We report results on the use of Ti-Al alloys as such a diffusion barrier. Our results indicate that it maintains its structural integrity and electrical conductivity after the deposition of a lead-based ferroelectric stack at 650 degrees C. The electrical properties of the capacitors were measured through the barrier layer by making direct contact to the diffusion barrier. The properties of the capacitors measured by direct contact to the Ti-Al alloy show clearly the absence of an insulating interfacial layer. Transmission electron microscopy and Rutherford backscattering studies confirm that there is no oxidation of the conducting barrier and no reaction between it and the electrode. (C) 1999 American Institute of Physics. [S0003-6951(99)05302-4].
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收藏
页码:230 / 232
页数:3
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