Performance Improvement of Pi-gate SOI MOSFET Transistor using High-k Dielectric with Metal Gate

被引:3
作者
Rahou, Fatima Zohra [1 ]
Bouazza, A. Guen [1 ]
Bouazza, B. [1 ]
机构
[1] Univ Abou Bekr Belkaid Tlemcen, Fac Technol, Dept Elect & Elect Engn, Mat & Renewable Energy Res Unit, Tilimsen, Algeria
关键词
High-k dielectric; multi-gate SOI MOSFET; Pi-gate SOI MOSFET; short-channel effects (SCEs); Silvaco software; technology SOI;
D O I
10.1080/03772063.2015.1084898
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Pi-gate silicon-on insulator (SOI) MOSFET transistors have emerged as novel devices due to its simple architecture and better performance, better control over short-channel effects, and reduced power dissipation due to reduced gate leakage currents. As the oxide thickness scales below 2nm, leakage currents due to tunnelling increase drastically, leading to high power consumption and reduced device reliability. Replacing the SiO2 gate oxide with a high-k material allows increased gate capacitance without the associated leakage effects. In this paper, we present the results of a 3D numerical simulation of the Pi-gate SOI MOSFET transistor. 3D device structure, based on the technology SOI is described and simulated by using SILVACO TCAD tools, and we compare the electrical characteristics results for titanium nitride (TiN) fabricated on Al2O3 (k approximate to 9), HfO2 (k approximate to 20), and La2O3 (k approximate to 30) gate dielectric. Excellent dielectric properties such as high-k constant, low leakage current, threshold voltage, and electrical characteristics were demonstrated. From the simulation result, it was shown that HfO2 is the best dielectric material with metal gate TiN.
引用
收藏
页码:331 / 338
页数:8
相关论文
共 10 条
[1]   Electrical properties of SiO2/TiO2 high-k gate dielectric stack [J].
Bera, M. K. ;
Maiti, C. K. .
MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING, 2006, 9 (06) :909-917
[2]  
Jorgen W., 2004, MICROELECTRON ENG, V75, P389
[3]   Improved electrical and reliability characteristics of HfN-HfO2-gated nMOSFET with 0.95-nm EOT fabricated using a gate-first process [J].
Kang, JF ;
Yu, HY ;
Ren, C ;
Wang, XP ;
Li, MF ;
Chan, DSH ;
Yeo, YC ;
Sa, N ;
Yang, H ;
Liu, XY ;
Han, RQ ;
Kwong, DL .
IEEE ELECTRON DEVICE LETTERS, 2005, 26 (04) :237-239
[4]  
Masaru K., 2009, IEEE ELECTR DEVICE L, V30, P466
[5]  
Moreau M., 2010, THESIS
[6]  
Rahou Fatima Zohra, 2014, EUR SCI J, V10, P286
[7]  
Razavi P., 2013, THESIS
[8]  
Silvaco, 2010, ATLAS US MAN DEV SIM
[9]  
Tsividis Y., OPERATION MODELLING, V2nd
[10]   On the scaling issues and high-κ replacement of ultrathin gate dielectrics for nanoscale MOS transistors [J].
Wong, Hei ;
Iwai, Hiroshi .
MICROELECTRONIC ENGINEERING, 2006, 83 (10) :1867-1904