Hot-Carrier-Induced Reliability for Lateral DMOS Transistors With Split-STI Structures

被引：1

作者：

Lu, Li ^{[1
]}

Lin, Feng ^{[1
,2
]}

Ma, Shulang ^{[1
,2
]}

Yin, Zhibo ^{[1
]}

Sang, Yuanchang ^{[1
]}

Sun, Weifeng ^{[1
]}

Liu, Siyang ^{[1
]}

Su, Wei ^{[2
]}

机构：

[1] Southeast Univ, Natl ASIC Syst Engn Res Ctr, Sch Elect Sci & Engn, Nanjing 210096, Peoples R China

[2] CSMC Technol Corp, Proc Integrat Technol Res Ctr, Wuxi 214000, Jiangsu, Peoples R China

来源：

IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY | 2021年 / 9卷

基金：

中国国家自然科学基金;

关键词：

Logic gates; Stress; Degradation; Hot carriers; Reliability; Silicon; Electric fields; Split-STI; LDMOS; hot-carrier reliability; SHALLOW-TRENCH-ISOLATION; LDMOS; DEGRADATION;

D O I：

10.1109/JEDS.2021.3128755

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this work, four kinds of lateral double-diffused MOS (LDMOS) devices with different split shallow trench isolation (STI) structures (Device A: LDMOS with traditional split-STI, Device B: LDMOS with slope-STI, Device C with step-STI and Device D with H-shape-STI) have been fabricated and the hot-carrier reliabilities also have been investigated due to the serious environment they are endured. The maximum bulk current (I-bmax) stress and the maximum gate voltage (V-gmax) stress have been carried out and the inner mechanism of device degradation have been investigated successfully. With the assistance of the T-CAD simulation tools, it is found that the main damage point locates at the STI conners with a mount of interface states generation, inducing serious degradation for these four devices. The Device D owns high hot-carrier reliability due to its special structure with narrow split-STI. The worst device is Device C because of the presence of extra STI damage point. Finally, a mechanism verification, the charge pumping (CP) method has been applied to better understand this work.

引用

页码：1188 / 1193

页数：6

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