Oscillation frequency in CML and ESCL ring oscillators

被引：35

作者：

Alioto, M ^{[1
]}

Palumbo, G ^{[1
]}

机构：

[1] Univ Catania, Dipartimento Elettr Elettr & Sistemist, I-95125 Catania, Italy

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS | 2001年 / 48卷 / 02期

关键词：

bipolar transistor circuits; circuit modeling; CMOS integrated circuits; current mode logic; emitter coupled logic; frequency estimation; high-speed integrated circuits; oscillators;

D O I：

10.1109/81.904885

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper a model to accurately evaluate even in a pencil-and-paper manner the oscillation frequency of a ring oscillator made up by a CML or ESCL differential gate is proposed. The model allows us to simply estimate the oscillation frequency changes due both to the bias current change and to process tolerances. The model was validated by Spice simulations on both 6- and 20-GHz technologies for the CML ring oscillator, and on 0.8-mum CMOS process for the ESCL ring oscillator. The estimated oscillation frequency agrees with the simulated one. Indeed, average errors lower than 10% were found.

引用

页码：210 / 214

页数：5

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