In this paper, a sensitive and simple technique for parasitic interconnect capacitance measurement with 0.01fF or 10 aF sensitivity is presented. This on-chip technique is based upon an efficient test structure design. No reference capacitor is needed. The measurement itself is also simple; only a DC current meter is required. We have applied this technique to extract various interconnect geometry capacitances, including the capacitance of a single Metal 2 over Metal 1 crossing, for an industrial double metal process.