Characterization and Analysis of Gate-All-Around Si Nanowire Transistors for Extreme Scaling

被引：12

作者：

Huang, Ru ^{[1
]}

Wang, Runsheng ^{[1
]}

Zhuge, Jing ^{[1
]}

Liu, Changze ^{[1
]}

Yu, Tao ^{[1
]}

Zhang, Liangliang ^{[1
]}

Huang, Xin ^{[1
]}

Ai, Yujie ^{[1
]}

Zou, Jinbin ^{[1
]}

Liu, Yuchao ^{[1
]}

Fan, Jiewen ^{[1
]}

Liao, Huailin ^{[1
]}

Wang, Yangyuan ^{[1
]}

机构：

[1] Peking Univ, Beijing 100871, Peoples R China

来源：

2011 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC) | 2011年

关键词：

LOW-FREQUENCY NOISE; CARRIER TRANSPORT; SOLAR-CELLS; MOSFETS; RELIABILITY; IMPACT; VARIABILITY; STRESS; FINFET; MODEL;

D O I：

10.1109/CICC.2011.6055334

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The gate-all-around (GAA) silicon nanowire transistor ( SNWT) is considered as one of the best candidates for ultimately scaled CMOS devices at the end of the technology roadmap. This paper reviews our recent work on the characterization and analysis of this unique one-dimensional nanowire-channel device with three-dimensional surrounding-gate from experiments and simulation, including carrier transport behavior, parasitic effects, noise characteristics, self-heating effect, variability and reliability, which can provide useful information for the GAA device hierarchical modeling and device/circuit co-design.

引用

页数：8

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