Hardware Efficient AES for Image Processing with High Throughput

Nowdays, image processing is applied to send an enhanced image in all applications including forensics, robotics, military communications. However, these applications have a additional overhead of image security. AES is one of the high speed technique which is used widely against various attacking techniques inspite of its high computational complexity. In this paper we propose the novel implementation of AES(Advance encryption standard) algorithm with reduced coding complexity and enhanced throughput by parallel processing of the key expansion technique. In addition, proposed approach also reduces the hardware required for implementation of AES. Algorithm is implemented on Xilinx virtex-6 using Questasim 10.0 b and further the encryption and decryption of image is simulated in MATLAB 2011a.