An Embedded Dynamic Voltage Scaling (DVS) System Through 55 nm Single-Inductor Dual-Output (SIDO) Switching Converter for 12-Bit Video Digital-to-Analog Converter

被引:11
作者
Chou, Wen-Shen [1 ]
Huang, Tzu-Chi [1 ]
Lee, Yu-Huei [1 ]
Yang, Yao-Yi [1 ]
Su, Yi-Ping [1 ]
Chen, Ke-Horng [1 ]
Huang, Chen-Chih [1 ]
Lin, Ying-Hsi [1 ]
Lee, Chao-Cheng [1 ]
Wen, Kuei-Ann [1 ]
Hsu, Ying-Chih [1 ]
Peng, Yung-Chow [1 ]
Hsueh, Fu-Lung [1 ]
机构
[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu, Taiwan
关键词
Single-inductor dual-output (SIDO); digital to analog converter (DAC); DC-DC converter; dynamic voltage scaling (DVS); least significant bit (LSB); differential nonlinearity (DNL); integral nonlinearity (INL); spurious free dynamic range (SFDR); CURRENT-STEERING DAC; 14-BIT;
D O I
10.1109/JSSC.2012.2191331
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper proposes a 55 nm CMOS 12-bit current- steering video digital-to-analog converter (DAC) directly powered by the single-inductor dual-output (SIDO) switching converter to compose a dynamic voltage scaling (DVS) system and improve the power efficiency. Dual-DVS control in both digital and analog circuits can effectively reduce power consumption. With various supply voltages, the video DAC can meet several different specifications in the power optimized (PO) mode. Furthermore, for DAC, the proposed 3S method, including finger separating, splitting and shifting, achieves good differential nonlinearity (DNL) performance to 0.78/0.4 least significant bit (LSB) and integral nonlinearity (INL) 1.3/1.0 LSB (with/without SIDO converter) without additional calibration. It also suppresses the switching noise interference from the SIDO converter. Moreover, for SIDO converter, the cross-regulation performance is greatly improved in both transient and steady state to achieve lowest interference for the analog supply. The total power efficiency can be improved up to 11.5% and 28% in the DVS and the PO mode. The SIDO supplied DAC with the dual-DVS function achieves 69.88 dB spurious free dynamic range (SFDR) at the 1 V output swing and 1 MHz input. The proposed intrinsic 12-bit DAC and SIDO converter achieve high definition video DAC performance with the benefit of area and energy efficiency.
引用
收藏
页码:1568 / 1584
页数:17
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